The present invention relates to a starting circuit, and, more particularly, to a starting circuit which produces a starting signal for initializing an internal circuit in a semiconductor integrated circuit device.
FIG. 1 shows a conventional starting circuit 51 in a semiconductor integrated circuit device 100. The starting circuit 51 receives power from a high potential power supply Vcc1 and a low potential power supply Vss.
The starting circuit 51 comprises a voltage-dividing circuit 52, a first stage section 53 and a waveform shaping circuit 54. The voltage-dividing circuit 52 includes resistors R1 and R2 connected in series between the high potential power supply Vcc1 and the low potential power supply Vss (0 V). The voltage-dividing circuit 52 supplies the first stage section 53 with a voltage Vn11 generated by dividing the high potential power supply voltage Vcc1 in accordance with the ratio of the resistance values of the resistors R1 and R2.
The first stage section 53 includes a resistor R3 and an N-channel MOS transistor (hereinafter simply referred to as an NMOS transistor) TN1 connected in series between the high potential power supply Vcc1 and the low potential power supply Vss. The divided voltage Vn11 is supplied to the gate of the NMOS transistor TN1 and the NMOS transistor TN1 goes on or off according to the level of the divided voltage Vn11. When the NMOS transistor TN1 goes off, the first stage section 53 supplies the waveform shaping circuit 54 with an H level (high potential power supply level) signal S11. When the NMOS transistor TN1 goes on, the first stage section 53 supplies the waveform shaping circuit 54 with an L level (low potential power supply level) signal S11.
The waveform shaping circuit 54 includes a plurality (for example, two) of inverter circuits 55 and 56 connected in series. The first-stage inverter circuit 55 receives the signal S11 from the first stage section 53. The waveform shaping circuit 54 waveform-shapes the signal S11 to produce a starting signal STTZ and supplies it to an internal circuit 57.
When the level of the external power supply (high potential power supply Vcc1) supplied to the semiconductor integrated circuit device 100 starts rising from the off state, a current starts flowing in the resistor R3 which forms a constant current source. At this time, the divided voltage Vn11 from the voltage-dividing circuit 52, as shown in FIG. 2, rises in proportion to the rise of the external power supply voltage Vcc1. Because the divided voltage Vn11 does not exceed a threshold voltage Vthn1 of the NMOS transistor TN1 until time t1, the NMOS transistor TN1 is maintained in the off state. Accordingly, the first stage section 53 supplies the H level signal S11 to the waveform shaping circuit 54 and the starting signal STTZ is set at the H level. In response to a high starting signal STTZ, the internal circuit (including a flip-flop circuit and a latch circuit) 57 is initialized.
Further, when the high potential power supply Vcc1 rises and the divided voltage Vn11 exceeds the threshold voltage Vthn1 of the NMOS transistor TN1 after time t1, the NMOS transistor TN1 is turned on. Consequently, the waveform shaping circuit 54 outputs a low starting signal STTZ. The initialization of the internal circuit 57 is completed in response to the trailing edge of the starting signal STTZ. Subsequently, when the high potential power supply Vcc1 becomes stable at a normal operating voltage (at which the internal circuit 57 operates normally), the starting circuit 51 holds the starting signal STTZ at the L level. Accordingly, unless the high potential power supply Vcc1 falls below a predetermined value again, the internal circuit 57 is not reinitialized. Thus, in the semiconductor integrated circuit device 100, the internal circuit 57 is initialized with the starting signal STTZ of the starting circuit 51 at power-on and malfunctioning of the internal circuit 57 is prevented.
If the time t1 at which the NMOS transistor TN1 goes on is earlier than the time at which the initialization of the internal circuit 57 is normally completed, the internal circuit 57 (i.e., the semiconductor integrated circuit device 100) malfunctions. Accordingly, the ratio of resistance values of the resistors R1 and R2 is set so that the divided voltage Vn11 may exceed the threshold voltage Vthn1 along with the rise of the high potential power supply voltage Vcc1 and the time t1 may be later than the time at which the initialization of the internal circuit 57 is normally completed.
Moreover, the threshold voltage Vthn1 of the NMOS transistor TN1 varies widely in a range from the maximum threshold voltage Vthn1max to the minimum threshold voltage Vthn1min due to unevenness in the chip manufacturing process. Therefore, the ratio of resistance values of the resistors R1 and R2 is set so that the divided voltage Vn11 may exceed the maximum threshold voltage Vthn1max of the NMOS transistor TN1. The time at which the divided voltage Vn11 exceeds the minimum threshold voltage Vthn1min of the NMOS transistor TN1 is defined as t2. The ratio of values of resistance of the resistors R1 and R2 is set so that the time t2 may be later than the time at which the initialization of the internal circuit 57 is normally completed.
In recent years, lower voltage power supplies have been replacing high voltage power supplies, and, as shown in FIG. 2, a high potential power supply Vcc2 having a lower voltage level than the high potential power supply Vcc1 is used as an operating power supply. However, in using the power supply Vcc2, the resistors R1 and R2 having the resistance values set for the high potential power supply Vcc1 are not suitable. Specifically, because a divided voltage Vn12 at which the high potential power supply voltage Vcc2 is divided does not exceed the maximum threshold voltage Vthn1max, the NMOS transistor TN1 does not go on. Accordingly, the starting signal STTZ does not fall to the L level and the initialization of the internal circuit 57 is not completed.
Therefore, the ratio of resistance values of the resistors R1 and R2 is changed so that a divided voltage Vn13 of the power supply Vcc2 may exceed the maximum threshold voltage Vthn1max. Accordingly, the starting circuit 11 can output the L level starting signal STTZ.
However, due to the variation in the ratio of resistance of the resistors R1 and R2, the time t3 at which the divided voltage Vn13 exceeds the minimum threshold voltage Vthn1min is reached more quickly. Accordingly, before the initialization of the internal circuit 57 is normally completed, the starting signal STTZ may fall. In other words, if the time t3 at which the starting signal STTZ falls to the L level is too quick and the initialization of the internal circuit 57 is not completed normally, a malfunction may occur in the semiconductor integrated circuit device 100. Consequently, irrespective of how the ratio of resistance of the resistors R1 and R2 is set, the starting circuit 51 cannot produce the starting signal STTZ which falls at the time at which an arbitrary semiconductor integrated circuit device 100 is normally initialized.
It is an object of the present invention to provide a starting circuit which produces a starting signal will surely initialize an internal circuit of a semiconductor integrated circuit device.
In one aspect of the present invention, a starting circuit is provided that operates by receiving power from high potential and low potential power supplies. The starting circuit includes a first transistor having a threshold voltage within a predetermined range. The first transistor receives a control voltage generated from the high potential and low potential power supplies and produces a signal from the time when the high potential power supply voltage starts rising to the time when the control voltage rises to the first transistor threshold voltage. A correction circuit is connected to the first transistor and adjusts the control voltage in accordance with the threshold voltage of the first transistor.
In another aspect of the present invention, a starting circuit is provided which operates by receiving power from high potential and low potential power supplies. The starting circuit includes a first transistor having a threshold voltage within a predetermined range. The first transistor receives a control voltage generated from the high potential and low potential power supplies and produces a signal from the time when the high potential power supply voltage starts rising to the time when the control voltage rises to the first transistor threshold voltage. A correction circuit is connected to the first transistor adjusts the control voltage in accordance with the threshold voltage of the first transistor. A voltage-dividing circuit divides the voltage of the high and low potential power supplies and generates the control voltage. The voltage-dividing circuit includes a first plurality of resistors connected in series between the high and low potential power supplies. The control voltage is determined by the ratio of the resistance values of the first plurality of resistors. The correction circuit includes a correction voltage-dividing circuit having a second plurality of resistors connected in series between high potential and low potential power supplies. The ratio of resistance values of the second plurality of resistors differs from the ratio of resistance values of the first plurality of resistors. The correction circuit includes a plurality of switching elements for selecting one of a divided voltage generated by the second plurality of resistors and the divided voltage of the voltage-dividing circuit and supplying the selected divided voltage to the first transistor as the control voltage.
In yet another aspect of the present invention, a semiconductor integrated circuit device is provide that includes a starting circuit which operates by receiving power from high potential and low potential power supplies. The starting circuit includes a first transistor having a threshold voltage within a predetermined range. The first transistor receives a control voltage generated by the high potential and low potential power supplies and generates a signal from the time when the high potential power supply voltage starts rising to and the time when the control voltage rises to the first transistor threshold voltage. A correction circuit is connected to the first transistor and adjusts the control voltage in accordance with the threshold voltage of the first transistor. A Waveform shaping circuit waveform-shapes the signal from the first transistor and generates a starting signal. An internal circuit is connected to the waveform shaping circuit and performs the initialization operation in response to the signal.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.